1. Field of the Invention
The present invention relates to a semiconductor device and a display device such as an electro-optic display having the same.
2. Description of the Related Art
There is an active matrix type thin film transistor (hereinafter, referred to as the TFT) serving as a switching element in a semiconductor device, and there is an electro-optic display device for the display device (such as a liquid crystal display device or an EL (Electro-Luminescence) display device) having the TFT. Since the electro-optic display device has characteristics of low power consumption and being thin, it is increasingly applied to a product as a flat panel display, instead of a CRT (Cathode Ray Tube).
Recently, brightness of a backlight increases, a TV screen becomes large, and definition of a small display becomes high in a mobile computer such as a mobile phone, so that the backlight is required to be further shielded in a TFT structure, and resistance of a line material of a semiconductor device for the display device is required to be further lowered.
A detailed description will be made of the backlight shielding in the TFT structure. According to a conventionally used TFT structure, a Si semiconductor layer including various kinds of silicon (Si) semiconductor films extrudes from an outer periphery of a gate electrode in a planar view. However, as the brightness of the backlight increases, a light leak current increases in the Si semiconductor layer, so that it is proposed that the Si semiconductor layer is prevented from being irradiated with light by arranging the Si semiconductor layer on an inner side of the gate electrode.
Next, a detailed description will be made of the lowering of the resistance in the line material. As a line material of the semiconductor device for the conventional display device, a high melting point metal material such as metal of titanium (Ti), chrome (Cr), molybdenum (Mo), tantalum (Ta), or tungsten (W) or an alloy mainly including the above metals is used in general. The above high melting point metal material is preferably used as the electrode material for the semiconductor device because an interface diffusion reaction is hardly generated in a connection interface with the Si semiconductor layer. However, since a specific resistance value of the high melting point metal material is 12 to 60 μΩ·cm in general, the high melting point metal material is not suitable for the electrode material for the semiconductor device under present circumstances.
Thus, aluminum (Al) or an aluminum-based alloy attract attention as the line material of the semiconductor device for the display device because the alloy is low in specific resistance and can be easily patterned into the line.
However, it is widely known that an Al film and an Al alloy film (hereinafter, referred to as the “Al alloy film and the like”) cause an excessive mutual diffusion reaction in a connection interface with a Si semiconductor film or a Si-based film (hereinafter, referred to as the “Si semiconductor film and the like”) and thus its electric characteristics deteriorate. Therefore, in the case where the Al alloy film and the like and the Si semiconductor film and the like are electrically connected, it is proposed that a burrier layer including the above high melting point metal material (hereinafter, referred to as the “high melting point metal burrier layer”) is interposed between them to prevent the electric characteristics from deteriorating.
In addition, in the electro-optic display device for the display device, an indium oxide series film generally used as its transparent pixel electrode material, such as an ITO (Indium Tin Oxide) film including indium oxide and tin oxide is connected to a line film (such as an Al alloy film). However, since the same interface diffusion reaction as that with the above Si semiconductor film is caused in a connection interface between the Al alloy film and the ITO film, it is proposed that the high melting point metal burrier layer is interposed between the Al alloy film and the transparent pixel electrode, similar to the above when they are electrically connected.
Each of Japanese Patent Application Laid-Open No. 6-236893, Japanese Patent Application Laid-Open No. 7.30118, and Japanese Patent Application Laid-Open No. 8-62628 discloses a technique to interpose the high melting point metal burrier layer between the low resistance Al alloy film and the like serving as the source and drain electrodes, and the Si semiconductor film and the like, as one example of the above technique. According to the technique, the low resistance Si film in which an impurity is added to Si (hereinafter, referred to as the “ohmic low resistance Si film”) or the ITO film is directly connected to the high melting point metal burrier layer including Cr, Mo, Ti, or Zr (zirconium) and then a low resistance Al series metal is formed on the high melting point metal burrier layer.
Each of Japanese Patent Application Laid-Open No. 2003-89864 and Japanese Patent Application Laid-Open No. 2008-10801 also discloses a configuration to prevent the interface diffusion reaction in the interface between the Al alloy film and the ITO or Si to obtain preferable electric characteristics (contact characteristics) of the interface, similar to the above technique. More specifically, Japanese Patent Application Laid-Open No. 2003-89864 discloses a technique to improve the contact characteristics by directly connecting an Al alloy film containing a predetermined amount of nickel (Ni) to each of the ITO film and the Si semiconductor film. In addition, Japanese Patent Application Laid-Open No. 2008-10801 discloses a technique in which an AlNi alloy film is used as the Al alloy film to improve the contact characteristics between the AlNi alloy film and the ITO film. In addition, Japanese Patent Application Laid-Open No. 2008-10801 discloses a technique in which a SiAlNi alloy film is connected to the Si semiconductor film with a layer containing nitrogen (N) in Si interposed therebetween to improve the contact characteristics between them. With the techniques disclosed in Japanese Patent Application Laid-Open No. 2003-89864 and Japanese Patent Application Laid-Open No. 2008-10801, at least a step of forming the high melting point metal burrier layer between the Al alloy films, and the ITO film or the Si semiconductor film can be omitted.
However, according to Japanese Patent Application Laid-Open No. 6-236893, Japanese Patent Application Laid-Open No. 7-30118, and Japanese Patent Application Laid-Open No. 8-62628, the high melting point metal burrier layer is formed to prevent the diffusion reaction in the interface between the Al alloy film and the like and the Si semiconductor film and the like, so that more steps of forming and etching the film are needed, which complicates a production process. As a result, the problem is that production capability is lowered. In addition, since unevenness is generated in a shape of an etched cross-section due to a difference in etching speed between the Al alloy film and the high melting point metal material, and due to a difference in side etching amount proceeding in a lateral direction at the time of etching, so that fine work is difficult to perform. Furthermore, the unevenness in the shape of the etched cross-section causes deterioration in coverage characteristics of a film formed as an upper layer. Thus, regarding the structure and method to interpose the high melting point metal burrier layer between the Al alloy film and the like and the Si semiconductor film and the like, it is difficult to produce the semiconductor device having high quality and high reliability.
In addition, when the techniques of Japanese Patent Application Laid-Open No. 2003-89864 and Japanese Patent Application Laid-Open No. 2008-10801 are used, the inventors of the present invention have found that there is a defect in an on current (Ion) that is a current flowing at an on time of a switching operation and an off current (Ioff) that is a leak current flowing at off time thereof.
More specifically, a Si semiconductor layer including the above ohmic low resistance Si film doped with phosphorus, and a Si semiconductor film in which a channel is formed based on a gate voltage (hereinafter, referred to as the “Si semiconductor active film”) is wholly or partially arranged in an inner side of the gate electrode so that the Si semiconductor layer is not irradiated with light from the backlight.
Thus, similar to the technique in Japanese Patent Application Laid-Open No. 2003-89864, the AlNi alloy film is directly connected to the Si semiconductor layer, as the source and drain electrodes of the TFT having the Si semiconductor layer, Just after this structure is formed, the mutual diffusion reaction is not recognized in each of the connection interface between the AlNi alloy film and the ohmic low resistance Si film, and the connection interface between the AlNi alloy film and the Si semiconductor active film. However, when this structure is subjected to a heat treatment (held in the air or a nitrogen gas atmosphere for about 30 minutes), the mutual diffusion reaction between Al and Si gradually proceeds, and when it is subjected to a heat treatment under the air or the nitrogen gas atmosphere at a temperature exceeding 250° C., the mutual diffusion reaction is recognized at a light microscopic level.
Meanwhile, when the structure is subjected to a heat treatment at a little lowered temperature (200° C. or more), noticeable mutual diffusion reaction is not recognized at the light microscopic level, but obvious deterioration is recognized in TFT characteristics when the electric characteristics of the TFT (TFT characteristics) are measured. More specifically, one digit or more increase in the above Ioff is recognized in the general Id (drain current)-Vg (gate voltage) characteristics of the TFT. It is supposed that this is because minute mutual diffusion which cannot be observed at the light microscopic level is partially generated in the connection interface between Al and Si.
Next, in a case where the configuration in which the N containing layer is formed between the AlNi alloy film and the ohmic low resistance Si film as disclosed in Japanese Patent Application Laid-Open No. 2008-10801 is subjected to a heat treatment at 300° C. or more, mutual diffusion reaction is not recognized between them, but mutual diffusion reaction (noticeable deterioration in electric characteristics in the TFT) is recognized in the interface between the AlNi alloy film and the Si semiconductor active film. As a specific phenomenon, Ioff increases to three digits or more and Ion decreases to about 50% of that provided when the high melting point metal burrier layer is formed. In addition, noticeable deterioration is recognized in on characteristics due to the heat treatment. More specifically, as compared to Ion just after the structure is formed, Ion after the heat treatment at 300° C. decreases to up to 50%.
However, the process for producing the active matrix TFT substrate for the general display device includes a treatment performed at a process temperature of 200° C. or more, or about 300° C. in general. Therefore, the above semiconductor device cannot be substantially used for the display device in view of heat resistance.